(1) Field of the Invention
The present invention relates to a data processing system wherein data prefetch is carried out, and a data processing device which is used in the system, having a function for prefetching data, and including a buffer memory wherein prefetched data is temporarily stored. The data which is prefetched includes commands and parameters which accompany respective commands. The parameters include numerical information, and are respectively processed in accordance with the corresponding commands.
The present invention is particularly advantageous for a data processing device which is used in a data processing system, which is connected to a common bus, and which shares the use of the common bus with other bus masters such as a central processor. Further, the present invention is applicable to a co-processor which is provided to take over and perform a part of the work of a central processor to enhance the capability of the central processor, and to a co-processor system which contains the above co-processor therein. Typical examples of such co-processors are an image processor and an arithmetic processor. In addition, the above co-processor may be constructed within a LSI chip as a peripheral LSI which cooperates with a microprocessor unit (MPU).
(2) Description of the Related Art
In data processing devices which process data, the data which is to be processed is supplied from a memory under control of a central processor, or is fetched from the memory by the data processing device itself, for example, by a DMA operation. In the data processing device having a function for prefetching data, the prefetched data is temporarily stored in a command and parameter buffer memory which is provided therein; in both cases the data is supplied under control of a central processor, and is prefetched by the data processing device itself.
In a data processing system wherein a common bus is shared by a plurality of bus masters, a bus arbitration is carried out by a bus arbiter for controlling use of the common bus by the plurality of bus masters, and it takes a considerable time to carry out the operation of the bus arbitration. During the operation of the bus arbitration, data transfer cannot be carried out using the bus. Therefore, when the frequency of the bus arbitration increases, the efficiency regarding the use of the bus, and thus the efficiency of the system, is lowered.
Thus, when the above data processing device, having a function for prefetching data, is incorporated in the above data processing system wherein a common bus is shared by a plurality of bus masters, reduction of the frequency of the prefetch operation is required to prevent the lowering of the efficiency of the system.
However, in the prior art, the above data prefetch in the data processing device is carried out every time a vacancy for storing new data is generated in the command and parameter buffer memory. The vacancy in the command and parameter buffer memory is generated every time an amount of data is read out from the command and parameter buffer memory, and is processed in an executing portion of the data processing device. When the above memory, wherein the data to be processed is stored, is connected through the above common bus, operations for obtaining an allowance to use the bus with regard to the bus arbiter, are carried out every time before the beginning of the prefetch operation. Therefore, in the conventional data processing device, the frequency of bus arbitration is increased by the above prefetch procedure.
In addition, in the prior art, the prefetch is carried out simply in the order of successive addresses in the memory wherein the data to be processed is stored, since, generally, the data to be processed is stored in the order of the processing. However, the data may include a branch command. When a branch command is processed in the data processing device, in most cases, the data which is to be processed in the next step is not the data which is stored in the address next to the branch command in the above memory address, and therefore, is not the data which has been prefetched following the branch command and stored in the command and parameter buffer memory. Namely, when a branch command appears in the data which is to be processed, the prefetched data following the branch command is, in most cases, useless. This means that useless prefetch operations and the useless bus arbitrations are carried out in the conventional data processing device, and these useless bus arbitrations lower the efficiency of the system.
Further, generally, the above data includes commands, each of which instructs what kind of processing is to be carried out, and one or more parameters which accompany the command and are to be used for the processing. Accordingly, in the prior art, the data which is fetched in the data processing device is comprised of a succession of pairs of a command and accompanying set of parameters. However, the pairs including the same command and different parameters, often are successively fetched. The fetched command is decoded at the first stage of the processing of each command in the data processing device even while data (the above pairs) including the same commands are successively processed. It is not desirable to repeat the prefetch and decoding of the same command, in view of the above-mentioned bus efficiency and the efficiency of the data processing device itself.